1. Field of the Invention
The present invention relates generally to data caches, and in particular to methods and mechanisms for optimizing a system cache located in a memory controller.
2. Description of the Related Art
Modern day mobile electronic devices often include multiple components or agents sharing access to one or more memory devices. These multiple agents may make large numbers of requests to memory, and as the number of these requests increases, the power consumption of the device increases, which limits the battery life of the device. One approach for reducing power consumption is to try to reduce the number of times that off-chip memory is accessed by caching data in or near the processor.
Conventional caches are typically coupled to or nearby a processor and store data that is frequently accessed by the processor to reduce latency. In a conventional cache, data may be retained in the cache based on the temporal locality of accesses. For example, when a line is allocated in the cache, the more times the line is referenced, the more difficult it becomes to have this line replaced. However, conventional caches are not designed for storing data that is accessed multiple times when the accesses are widely spaced in time. Such data would tend to get evicted in a traditional cache. Caches may also receive partial write requests that update less than a full cache line. Processing partial write requests that miss in the cache can be a challenge because these misses consume memory bandwidth and power.